1. Field of the Invention
The present invention relates to a transversal filter used in processing a received signal in a digital subscriber line interface apparatus (ISDN interface transceiver) for transmitting high-speed digital data in a transmitting and a receiving direction alternatively or simultaneously by using a metallic pair cable which forms an existing telephone subscriber line, and more specifically to a decimation filter for removing high frequency noise from digital data converted at a frequency much higher than the basic sampling frequency and at a lower precision than required, and for converting the result to high precision digital data at a speed lower than one or two times the speed at the basic sampling frequency and to a pulse shaping filter for shaping an isolated pulse response by shaping the waveform of a received signal so that a sampling timing of the data can be controlled.
2. Description of the Related Art
In order to make a digital communication network such as an ISDN used widely, a digital subscriber line transmission system has been developed for transmitting high-speed digital data by using existing metallic cable which is currently being used for transmission of a voice band signal. In this case, it is necessary to properly deal with inter-symbol interference distortion caused by variations in transmission loss due to a difference in distance between subscriber lines, limitations of pass band and reflection by bridge taps (BT) with an open end which exists in an existing subscriber line. As a transmission system, a ping-pong transmission system for alternatively performing transmission and reception in a time divisional manner and an echo-canceler system for performing transmission and reception simultaneously by using a hybrid circuit and an echo-canceler have been developed.
An over-sampling A/D converter has been used for receiving a signal in a digital subscriber line transmission interface device for simultaneously or alternately transmitting high speed digital data in two-way (sending/receiving) directions using metallic pair cables, that is, existing telephone subscriber lines.
The above described high speed digital subscriber line transmission interface device transmits a four-value amplitude code represented by values .+-.1 and .+-.3, for example, at a transmission speed of 80 Kilobaud.
A signal attenuated and distorted in its waveform by the loss characteristics of metallic pair cables is digitized by an A/D converter for receiving a signal from a corresponding unit so that a digital process can correct the attenuation and the deformation in its waveform.
Furthermore, the relation between the size of hardware and the conversion precision of the A/D converter has required that an over-sampling A/D converter be used in a unit for transmitting 4-value codes at a transmission speed of about 80 Kilobaud.
An over-sampling A/D converter converts data to a digital signal more coarse than required precision at a sampling frequency much higher than a basic sampling frequency depending on baud rate frequency of a signal. The resultant signal is passed through a low-pass digital filter so that high frequency noise can be removed from the signal and then the signal can be converted to high-precision digital data at a speed lower than one or two times the speed at the basic sampling frequency. This filter is commonly referred to as a decimation filter.
Normally, a decimation filter used in the above described conventional digital subscriber line transmission interface device can be a transversal filter with a transfer function (representing input data/output data) indicated by the following equation (1). The characteristics of the stop bands of the filter is that of a comb type filter in which the peaks of the loss characteristics are concentrated on m zero points occurring at equal intervals. The characteristic of the passing bands of this filter is that the loss is increases as the frequency gets higher, Therefore, a pulse shaping filter is required in the stage following this filter if the pulse waveform is to be flat or controlled at request. ##EQU1##
where z=exp (j2.pi.f/(nf.sub.s)), m=2 or 3, n indicates an over-sampling ratio, f.sub.s indicates the basic sampling frequency, and f indicates the frequency of a signal.
To adjust the timing of a received signal, a first precursor indicating an isolated pulse response characteristic of a received signal is used.
To use the first precursor in adjusting the timing as described above, the first precursor is positioned at the point where the sign of the isolated pulse response characteristic turns from negative to positive. Furthermore, it is desirable to maintain a post-cursor small enough to reduce the burden on the decision feedback equalizer in the following stage. The pulse shaping filter is used to determine a precursor and a post-cursor such that the isolated pulse response characteristic indicates the desired form.
Normally, a high-pass filter fop removing direct current components is provided in the stage following the pulse shaping filter. Since the filter can be operated at the basic sampling frequency, it is implemented by a digital signal processor together with the functions of the decision feedback equalizer, etc.
As shown in FIG. 1, the input part of the conventional digital subscriber line transmission interface device comprises a .DELTA..SIGMA. converter 1 in the over-sampling A/D converter, a decimation filter 2, a pulse shaping filter 3, and circuits 4 such as an echo-canceler, etc.
A received signal is applied to the .DELTA..SIGMA. converter 1 through a simple low-pass filter not shown in FIG. 1. The received signal is converted by the .DELTA..SIGMA. converter 1 to a 1-bit digital signal at an over-sampling frequency of 15.36 MHz, for example. These high speed data are converted to low-speed multi-bit data by the decimation filter 2 having the transfer function shown by equation (1). However, the speed is not as low as the baud rate because the filter should be operated at a frequency higher than double the baud rate to form a waveform of a precursor portion, etc. with the required precision. That is, the decimation filter 2 outputs data at least at double the baud rate and the basic sampling frequency of 80 KHz in the digital subscriber line transmission interface device, that is, at 160 KHz. A practical example of equation (1) is shown by the following equation (2). ##EQU2##
Since the numerator in equation (2) contains the term (1-z.sup.-1), equation (2) is a function without a denominator, indicating a transversal filter with 286 taps as shown by equation (3). 286 is the result of the expression (96-1).times.3+1. ##EQU3##
The zeros are triply overlapping and occur at equal intervals on the z plane as shown in FIG. 2 except the portion near the point where z=1.
On the other hand, the pulse shaping filter is a transversal filter with 6 to 8 taps operating at the frequency of double the baud rate. The output can be obtained at the baud rate, that is, 80 KHz.
The transfer function of the pulse shaping filter is obtained by the following equation (4), for example. ##EQU4##
where a.sub.0 through a.sub.7 are tap coefficients of a transversal filter.
FIG. 3 shows the loss frequency characteristics of the low-frequency portion of a filter composed of a conventional decimation filter and a conventional pulse shaping filter. The loss at 30-40 KHz is larger than that at DC. That is, there is a small gain at 30-40 KHz, and a frequency over 60 KHz ensures a stop frequency band at which the data does not pass through the filter due to the loss. Macroscopically, the higher the frequency is, the larger the attenuation becomes, gibing a maximum value around 7.68 MHz though not shown in FIG. 3.
The peak attenuation at intervals of 160 KHz shown in FIG. 3 is caused by the zero point of the decimation filter, and the other peaks are obtained by the zero points of the pulse shaping filter. The attenuation obtained at the peak at intervals of 160 KHz is larger than that obtained at any other point because the zero points of the decimation filter are triply overlapping.
Although a triply-overlapping zero point results in a locally large attenuation, the attenuation at the frequencies between two zero points is small. Therefore, it is not totally efficient from the view point of the reduction of noise, which is the object of a decimation filter. To reduce noise down to the level below a predetermined value, the scale, that is, the order, of the filter should be large enough.
FIG. 4 shows the configuration of a conventional decimation filter. Since the output of the .DELTA..SIGMA. converter 1 is represented by a value .+-.1, the calculation according to equation (3) is replaced with an addition or a subtraction of a tap coefficient. Besides, as an input signal is applied to the decimation filter at a frequency of 15.36 MHz, it is very difficult to repeat additions or subtractions without limit. Therefore, three adders are necessary according to the calculation 285/(15360/160)=2.97 to obtain an output at 160 KHz. Accordingly, the operation of equation (2) can be divided into three steps as indicated in the following equation (5). ##EQU5##
Each of the terms in equation (5) is executed by different hardware. FIG. 4 shows the hardware of a decimation filter. The operation of the first term of equation (5) is executed by the first stage S1 shown in FIG. 4, and the result of the operation is transmitted to register R2. Then, the operation of the second term of equation (5) is executed by the second stage S2 of the central part shown in FIG. 4. Likewise, the result of the operation is transmitted to register R3, and the remaining operation is executed by the rightmost third state S3 in the circuit with the result outputted as the decimation filter.
ROM M1 through ROM M3 in the circuit shown in FIG. 4 store tap coefficients which are read and added by selectors S1 through S3 respectively after being inverted (subtraction) or maintained as is (addition). The scale of the circuit is about 1,700 gates.
The decimation filter shown in FIG. 4 is explained in detail. ROM M1, selector S1, adder A1, and register R1 form a module for calculating the first term of equation (5). ROM M2, selector S2, adder A2, and register R2 form a module for calculating the second term of equation (5). ROM M3, selector S3, adder A3, and register R3 form a module for calculating the third term of equation (5).
Equation (5) is expressed in terms of Z.sup.-1, and the actual process is performed such that signal data Xi inputted at 15.36 MHz are multiplied by filter coefficients bi, and 288 such products are obtained and summed to form the output of the filter. Since the actual input is +1 or -1, a sum of products can be calculated by an adder. If an adder performs an addition in every cycle at 15.36 MHz, only 96 additions can be performed in the time period corresponding to 160 KHz. Therefore, three adders must be provided in parallel to obtain an output at 160 KHz. This is the reason why the calculation of the filter is divided into three terms. The first term of equation (5) performs an addition for the portion containing filter coefficients 0 through 95, the second term of equation (5) performs an addition for the portion containing filter coefficients 96 through 191, and the third term of equation (5) performs an addition for the portion containing filter coefficients 192 through 287.
In FIG. 4, ROM M1 stores filter coefficients 0 through 95, ROM M2 stores filter coefficients 96 through 191, and ROM M3 stores filter coefficients 192 through 287. If an input signal Xi is positive, a coefficient from a ROM is applied as is to an adder, and it is applied after being inverted if Xi is negative. The sum is fed back to the input part of the adder, and the addition is repeated 96 times.
Normally, selectors S4 and S5 apply the output of register R2 to adder A2 and apply the output of register R3 to adder A3. However, at every 96th cycle, selectors S4 and S5 apply the output of register R1 to adder A2 and the output of register R2 to adder A3. Likewise, the output of register R3 is outputted as the output of the filter. In this cycle, the route from register R1 to adder A1 is omitted, and adder A1 starts its addition at zero.
As a result, the contents of register R2 are obtained by adding the sum of the second term to that of the first term, and the contents of register R3 are obtained by adding the sum of the third term to those of the first and second terms. The sum of the 96th addition of register R3 indicates the result of the arithmetic operation according to equation (5). FIG. 5 shows the time chart of these operations.
FIG. 6 shows the configuration of the circuit of a conventional pulse shaping filter. It is a transversal filter, but different from the configuration shown in FIG. 4 in that the input signal of the pulse shaping filter (the output of the decimation filter) is composed of 18-bit 160 KHz data, not a 1-bit input as in the case of the decimation filter. The tap coefficients a.sub.0 through a.sub.7 of this filter require a precision of about 10 bits, and the operation of equation (4) is performed as a sum-of-products operation. Since a multiplier must be provided to obtain a product and the hardware scale of the multiplier has to be large, an output can be obtained in the circuit shown in FIG. 6 by storing 256 sorts of output data in the ROMs if each piece of input data comprises one bit, and by repeating additions 18 times by shifting by one bit the output corresponding to a digit of input data if each piece of the input data comprises 18 bits. The input of the pulse shaping filter is applied at 160 KHz, the output is obtained at 80 KHz, and one added is used for multiple uses. The scale of the circuit of the filter is indicated by 1500 gates not including ROMs.
The pulse shaping filter shown in FIG. 6 is used for performing the arithmetic operation of equation (4). The following equation can be obtained by rewriting equation (4) by using an input data series Xi (i=0, 1, . . . , 7). ##EQU6##
if Xi is a binary occupying 14 bits, it can be represented by the following equation. ##EQU7##
Xi can be substituted in the above equation. ##EQU8##
Since bij is 0 or 1, the Cij can be one of 2.sup.8 =256 values when an 8-tap transversal filter is used. The Cij corresponding to each sample of an input signal string can be sequentially outputted to an adder by storing 256 values in ROMs end reading Cij from ROM MA4 with bit data comprising 8-digit input signal data as an address.
In FIG. 6, eight consecutive signal data are stored in registers RA1 through RA8. For example, input data are provided to an address in ROM MA4 at 160 KHz sequentially from a lower order bit in each register. Thus, a corresponding Cij is outputted.
Next, a sum should be obtained after multiplying Cij by 2.sup.-j. For example, if data are processed starting from the lower order bit, then the output in register RA0 containing a sum is shifted towards the low-order side by one bit and a Cij corresponding to the next bit is added, Since the output of the filter is the sum of number-of-digits times of additions, the result is outputted after changing the direction of a selector.
Assuming that the frequency of the output is 80 KHz and that of the input is 160 KHz, the above described process is performed once at 80 KHz by shifting input data twice.
FIG. 7 is a coefficient map of a conventional filter comprising a conventional decimation filter and a pulse shaping filter, indicating the impulse response.
FIGS. 8 and 9 show the isolated pulse response characteristic of an output waveform when a signal pulse is applied after being transmitted through the long cable with 7.5 Km length and when the cable length is zero in the case where a filter comprises a conventional decimation filter and a pulse shaping filter as shown in FIG. 6.
The isolated pulse response characteristic indicated when a signal is applied after being transmitted through the long cable is obtained through a high-pass filter in response to the output of a pulse shaping filter. That is, the characteristic is obtained as a result of the process 1-D.
On the other hand, the isolated pulse response characteristic indicated when the cable length is zero is obtained after the process 1/(1-0.875D) in addition to the process 1-D, where D=z.sup.-1 =exp(-j2 .pi.f/80) and f indicates a frequency (KHz). Since a filter coefficient can be represented by 4 bits at maximum, the filter processes (1-D) or (1-D)/(1-0.875D) cause no problems in performing processes in a digital signal processing circuit having no multipliers in the following stages.
Since a conventional decimation filter aims at reducing high-frequency noise, its impulse response is that of a normal low-pass filter, and indicates a main response, exclusively as shown in FIG. 10. As the characteristics shown in FIG. 10 indicate no ringing before a main response, a precursor cannot be used to adjust timing.
The hardware containing a decimation filter followed by a pulse shaping filter in an over-sampling A/D converter of a conventional digital subscriber line transmission interface device requires a large scale circuit involving a total of about 3200 gates.
A digital signal processing circuit in the following stage for operating a high-pass filter, an echo-canceler, a decision feedback equalizer, etc. must be operated at a high speed of 15.36 MHz. However, it cannot involve a process in a decimation filter, nor in a pulse shaping filter because no adders are provided. If a multiplexer is provided, a pulse shaping filter can be operated, but requires 3000 or more gates for the circuit of a multiplexer. Thus, the scale of the circuit is required to be considerably large.
Therefore, a decimation filter and a pulse shaping filter must be realized as exclusive circuits, thereby preventing from being realized the reduction of the scale of the entire hardware and of the power consumption. Accordingly, small scale of decimation filter and pulse shaping filter circuits have been requested.
FIG. 11A shows an isolated pulse response of a transmission line up to the input of the decision feedback equalizer 4 when pulse shaping filter 3 is not provided. FIG. 11B shows a characteristic obtained by inserting the pulse shaping filter 3 and in and the characteristic of change from the negative to positive in the region around the precursor preceding the main cursor by 1 sampling period, the isolated pulse response amplitude being at its maximum at the main cursor. Then, a timing controller delays the sample timing when the precursor value C.sub.1 calculated at the decision feedback equalizer 4 is negative and advances the sample timing when the precursor value C.sub.1 is positive. A clock controlled by the timing controller is input to respective units as the operation clock.
A transversal filter with 7 to 9 taps is used for pulse shaping and it is considered that an operation with a frequency twice or three times the symbol frequency is required to perform pulse shaping completely. This is because control of the amplitude of a received signal only at every symbol period is not sufficient to perform pulse shaping completely and thus control of the amplitude of the received signal is considered to be performed at the middle point of the symbol period or at three points obtained by equally dividing the symbol period.
Therefore it is conventionally necessary that the frequency of the output of the decimation filter 2 is twice or three times the symbol frequency. The decimation filter 2 obtains the digital value with multiple bits by deleting a high frequency component of the signal obtained by performing 1 bit quantization at a high frequency which is 200 times the symbol frequency and thus should operate at a frequency near 200 times the symbol frequency and thus comprises a large scale transversal filter with 300 taps.
Therefore the decimation filter is formed of dedicated hardware. Generally speaking, the scale of hardware of the digital transversal filter has a strong relationship with the product of the frequency of the input data, the frequency of the output data and the number of taps. The greater the product becomes the larger the scale is. Accordingly the fact that the repetition frequency of the output data from the decimation filter 2 is twice or three times the symbol frequency makes it difficult to decrease the scale of the decimation filter. A higher repetition frequency of the output data of the decimation filter requires a higher operation of the filter and makes multiple use of the hardware difficult, thereby substantially increasing the scale of the circuit as well as the power consumption.